1. Field of the Invention
The invention generally relates to computer systems. More specifically, the invention relates to the structure and use of a translation lookaside buffer within a computer system capable of the speculative processing of memory accesses.
2. Description of Related Art
A translation lookaside buffer ("TLB") is commonly employed within a microprocessor for facilitating the translation of linear addresses to physical addresses for prompt memory access. FIG. 1 illustrates a portion of a conventional microprocessor architecture employing a TLB 10. TLB 10 is connected through a central processing unit ("CPU") bus 12 to an instruction fetch and issue unit 13, an address generation unit ("AGU") 14, a page miss handler ("PMH") 16, a data cache unit 17 ("DCU") and a system bus driver 18. Bus driver 18 is also connected through a system bus 20 to a main memory 22 and an input/output unit 21.
Numerous other functional elements of the conventional microprocessor architecture are, for clarity and brevity, not illustrated within FIG. 1. Rather, FIG. 1 merely illustrates a limited number of functional components sufficient to describe the operation of a TLB. The functional units illustrated in FIG. 1 may be interconnected by separate data busses, where appropriate. The TLB includes a separate data TLB ("DTLB") (not shown) and a separate instruction TLB ("ITLB") (not shown).
In use, instruction fetch and issue unit 13 generates instructions or commands for use in accessing data stored within main memory 22. The memory access instructions may specify that the data is to be loaded from main memory 22 or that data is to be stored within main memory 22. The instructions are received along the CPU bus 12 by AGU 14 which generates an address identifying the location of the data to be loaded or stored. When operating in "real" mode, AGU 14 generates the actual physical address of the data to be accessed within main memory 22. The physical address is then latched by DCU 17 which attempts to satisfy the memory instruction from internal cache lines. If the data subject to the memory access instruction is not contained within the internal cache lines of DCU 17, the instruction is merely routed through the system bus driver 18 to main memory 22 for directly accessing the physical address either to store data to the physical address or to load data from the physical address.
When operating in "protected" mode, AGU 14 generates a "linear" address which must first be converted to a physical address before main memory 22 may be accessed. PMH 16 performs a translation of the linear address received from AGU 14 to a physical address. Typically, PMH 16 performs a page table walk which includes a sequence of operations controlled by a state machine within PMH 16 to convert the linear address to a physical address. A wide variety of techniques have been developed for performing a page table walk to generate a physical address and such techniques will not be described in detail herein.
Most page table walk techniques are rather time consuming. To expedite the translation of linear addresses to physical addresses, TLB 10 provides a table relating selected linear addresses to physical addresses. More specifically, TLB 10 operates as a cache by storing a linear address and its corresponding physical address for several of the most recently accessed memory locations. Prior to performing a page table walk using PMH 16, the linear address generated by AGU 14 is transmitted to TLB 10 which determines whether internal registers of TLB 10 already contain a translation of the linear address to a corresponding physical address. If the address to be translated is contained within TLB 10, the corresponding physical address is merely output from TLB 10 for immediate processing by any functional unit requiring the physical address, such as DCU 17. If the translation for the linear address is not currently maintained within the TLB 10, then PMH 16 performs the above-described page table walk for generating the physical address. Typically, TLB 10 stores physical addresses for corresponding linear addresses for all of the most recently accessed pages of memory. If an address translation is not found within TLB 10, a page "miss" is said to have occurred and PMH 16 performs the address translation to remedy the page miss--hence the name "page miss handler."
FIG. 2 illustrates one entry 23 within TLB 10. As can be seen, the entry includes a linear address 24, a corresponding physical address 26 and one or more status bits 28. The status bits 28 may indicate, for example, whether the entry contains a valid translation.
In the foregoing description, it was assumed that any memory access generated by the microprocessor can be immediately executed once the physical address for the memory access has been determined. However, with certain microprocessor architecture's and for certain applications, a memory access must be deferred pending the resolution of one or more conditions. In such systems, once the physical address is determined, the memory access instruction cannot, or should not, be immediately executed. Such may occur, for example, in a microprocessor which is capable of generating "out-of-order" or "speculative" memory access operations. In an out-of-order microprocessor, memory access operations may be issued by instruction unit 13 in an order other than that which is defined by a software program. Out-of-order issuing of memory access instructions may be employed to enhance overall processor efficiency by exploiting any parallel processing capabilities of the microprocessor. When memory access operations are issued out-of-order, it may be necessary to hold one or more of the operations in abeyance pending execution of other, later issued, operations. For example, the execution of a memory access may require deferral until the resolution of a branch condition, such as an "If" statement.
In a microprocessor architecture capable of speculative processing, further efficiency is gained by performing a branch prediction upon the occurrence of any unresolved branch condition. Branch prediction allows commands subsequent to the branch to be speculatively processed pending resolution of the branch condition. In other words, for each branch condition the microprocessor predicts which branch is to be taken, then executes subsequent instructions speculatively. The ability to execute commands speculatively further exploits any parallel processing capability of a system by allowing at least some commands which depend upon a branch condition to be performed prior to actual resolution of the branch condition. General aspects of out-of-order and speculative processing are described in "Super Scalar Microprocessor Design" by Mike Johnson, Prentice-Hall, Inc. 1991.
As can be appreciated, numerous limitations exist as to which commands or instructions can be performed out-of-order and which can be performed speculatively. One possible limitation to the execution of instructions and commands is that actual memory accesses to main memory may require deferral until the execution of prior instructions or until the resolution of prior branch conditions. For example, it may be undesirable to perform a load from main memory based on a speculative load operation if the speculative load accesses memory mapped I/O.
Thus, in certain computer processors, such as out-of-order processors and speculative processors, it is desirable to store information identifying whether a memory access operation can be performed immediately or must be deferred pending the resolution of some condition, such as the resolution of any speculative antecedent conditions. It is also desirable to implement such a capability using one or more of the memory access functional units illustrated in FIG. 1. It is to this end that the present invention is directed.